Alain Mosnier

Open source projects:

• Author and maintainer of a SHA-256 implementation. Among others, it is being used in WinBtrfs, as well as in some industrial applications.
• After some basic and advanced courses in Haskell to improve my knowledge of functional programming, currently exploring the C++ ranges library (C++20, 23 and 26), which for instance enables more immutability and lazy evaluation, through a personal C++ project in the field of cryptography. Immutability, in particular, is generally considered as a way to drastically decrease the number of possible bugs. I will probably release the source code for that project at some point in the future.

Customer assignments:

• For several years, I have sucessfully been recommending and encouraging the broader adoption of modern C++ (up to C++20) in a large embedded software code base. I have in multiple practical cases demonstrated how it can be used to improve type-safety, and to provide compile time-configurability (through C++ templates and concepts), which allows a dramatic increase of code sharing between applications, without any performance impact. I have made extensive use of constexpr and static_assert to implement "compile time-unit tests", a very powerful mechanism made possible by modern C++.
• Refactored a solution for distribution of application messages over an SPI bus using unique pointers instead of manually allocated/deallocated buffers. Manual allocation/deallocation is error prone (risk of memory leaks) and is generally discouraged in modern C++. This implementation showed how standard unique pointers can be used even when dynamic allocation is based on ad-hoc memory pools (to avoid fragmentation). This refactoring also allowed the removal of a large number of lines of code with no loss of functionality, which decreases the maintenance cost.
• Design and implementation of a solution for application level message distribution between and single master and multiple slaves on a communication bus. A general model was designed, where multiple OS-threads on a master shall be able to communicate with multiple OS-threads running on multiple physical slaves. Enumerated message types are mapped at run time to true C++ types, enabling type-safety and avoiding bugs.
• In a project initiated to work around component shortage in a highly successful product, implementation of an MCU-based replacement for an FPGA. Two blocks are implemented:
  • A communication protocol master for an RS-485 multidrop bus.
  • Handlers for three SPI analog-to-digital converters.
  In both cases, the communication needs to be accurarely synchronized with PWM signals used for motor control via a three-phase H-bridge. The code is mostly written in C++17.
• Design and implementation of a generic thread-safe serial flash storage solution, with support for rotating logs and an arbitrary key-value store. The exact contents of the storage, the so-called "flash map", is configured at compile-time with the help of C++17 variadic templates. This is used to replace ad-hoc solutions in multiple applications, which allows the removal of several hundreds lines of code in each concerned application, without loss of functionality.
• Design and implementation of a solution to synchronize the real-time scheduler and data transmission of a slave to synchronization packets received from a bus master. The real time synchronization algorithm involves inducing the master period and dynamically adjusting the current slot length, within configurable margins. The synchronization of transmission involves optimal use of multiple peripherals (timer, DMA and UART). The code is written in C (update of legacy device drivers) and C++17.
• Refactoring of a torque handling module written in C and using static structures into configurable and reusable C++ classes. The primary goal was to correct multiple race conditions, among others due to incorrect handling of battery glitches, but at the same time, care was taken to make the objects adapatable to similar needs in the same application and in other similar applications. The result was a sucessful removal of multiple bugs, and the ability to replace multiple similar modules by shared classes. This was also an occasion to introduce more modern C++ (C++17) in the applications.
• Design and implementation of a bootloader for a Cortex-M MCU, as a workaround for a blocking issue introduced by the MCU vendor in a new revision of the MCU. The booloader shipped with the MCU has a critical bug which the vendor is unable to fix. Fortunately, there was enough free Flash memory to load an alternative bootloader during production, which emulates the vendor's SPI-based data protocol.
• Participation in the integration of a new digital torque transducer in an electrical nutrunner. The transducer is attached to the tap and rotates with it. This gives higher accurracy, but makes the transmission of electrical signals more challenging. A slip ring is used. The communication is asynchronous, half-duplex, over a single wire. Design and implementation of the data procotol for software update on master and slave. Design and implementation of a bootloader which runs from RAM. Design and implementation of the software solution for the reception of real time samples with a fixed frequency. Since there is no strict synchronization between the sender and the receiver, an adaptative algorithm was designed and implemented, based on a DMA circular buffer.
• Design and implementation of a solution to avoid race conditions in the detection and handling of battery connections/disconnections on a battery powered nutrunner. In particular, proper handling of series of glitches required the implementation of a specific real-time state machine. This is quite a typical example of a problem in which the lucky case is pretty much irrelevant in the design of a proper solution. Robustness can only be achieved by solving the worst case, at every step.
• Troubleshooting of Wi-Fi disconnection issues with a radio module provided by an external vendor. In order to prove that the issue was in the vendor's module, I isolated it by implementing a simple TCP client and server in Python on Raspberry Pi boards, and captured the air traffic in Wireshark.
• Design and implementation of a solution for retransmission of message segments over an SPI link. The purpose was to improve the robustness of transmission in case of ESD issues that lead to CRC errors. The main design criteria was minimization of the impact on CPU time, which was a scarce resource. The solution only used one additional bit of signaling on the link.
• Design and implementation of a solution for update of software on multiple sub-systems in a new embedded product. A master was implemented in C++ under Linux. Since the master only has direct contact with one of the slaves, a software update relay was implemented on that slave, in C++ under FreeRTOS. All communication between master, relay and slaves was based on SPI. One important design criteria was code sharing: the addition of a new slave only requires the development of a thin layer of adapter code.
• Design and implementation of an EEPROM emulation layer for NOR-flash chips. This involved studying ideas available from academia (Algorithms and Data Structures for Flash Memories, in particular), and developing the data structures and algorithms for reading, writing, and garbage collection. One of the main design criteria was reliable wear leveling. Unit testing was based on a RAM-emulated NOR-flash area, and was crucial in ensuring stability and reliability of the solution. The reference use case used an SPI flash chip, although the solution in itself made no assumptions on the available interface, which was accessed through an abstract API.
• Solved some real-time overrun issues in a distributed software oscilloscope module. The running time of the most time-critical run-to-completion function, running on a 16-bit DSP, was drastically reduced, from 28 microseconds to 6 microseconds.
• Design and implementation of an encryption solution for a 16-bit DSP. This was necessary to protect secret data located on an SD-card. I selected AES as the obvious state-of-the-art solution, and chose the tiny-AES-c implementation. Since no obvious value was available for the initialization vector (IV), I choose to use a cryptographically secure hash computed from a unique serial number. Since I found no SHA-2 implementation that was small enough for the 16-bit DSP, I created and published a public domain SHA-256 implementation on my own time, and used it for this solution. The SHA-256 implementation includes extensive unit tests that are automatically run on Travis.
• Design and implementation of a mutex solution for a custom scheduler on a 16-bit DSP. Special attention was given to starvation-freedom and performance.
• Performance optimization in a custom scheduler on a 16-bit DSP. This involved a modification of the scheduler's context switching algorithm.
• Implementation of various support tools in Python for the needs of the project team. These involved custom SD card partitioning and formatting, serial communication over USB, etc.
• Proposed and partly implemented the adaptation of a legacy binary protocol to support a new user level interface for an industrial process. This involved the prioritization of features, a clever reuse and extension of the existing protocol, as well as an incremental implementation and regression testing at every step, in order to timely deliver the functionality for a crucial demonstration to the customer.
• Design and implementation of a solution to store and retrieve critical records on an SD card over SPI in an industrial application. This involved some performance optimizations in order to meet the response time requirements, as well as wear testing over several million records.
• Design and implementation of a solution to update software on five distinct CPUs in a distributed embedded system from an SD card over SPI, while answering status requests from a PC application over a UART.

Customer assignments:

• Modelized the master of a real-time communication protocol over SPI as a finite state machine, leading to a refactoring of the code on both master and slave, in order to remove the causes of instability in behavior.
• Development of an emulator for a portable embedded industrial system, used in system tests. The emulator runs on a Windows or Linux PC (Qt-based), and is configurable via a text file. It can emulate an arbitrary number of embedded devices. It is able to receive a process description in binary format, and to produce process results according to a configurable schedule.
• Implementation of a Wi-Fi ad hoc bonding procedure on an industrial controller, for an embedded radio module. The interface to the radio module was a WPA supplicant under Linux.
• Design and implementation of a translator from a complex process parameter set to a set of binary process steps understood by an existing target embedded system. The translator runs on a Linux based industrial controller.
• Design and implementation of a protocol master for a custom asynchronous protocol in a distributed embedded system. On top of that protocol stack, I also implemented an application level protocol master in order to control an input/output device used to select an industrial process on a portable device and get feedback from it when the system runs it.
• Implementation of an algorithm to estimate torque from motor current and angular acceleration, for safety purposes. Computation of angular acceleration by double derivation of angular position was first implemented and tested.
• Design and implementation of control algorithms for an attachement with a mechanical stop on an existing portable industrial system. This included the implementation of a mechanical algorithm to compute a gear ratio.
• Specification, hardware/OS selection and implementation of a proof-of-concept for the controller unit of a next generation cash handling system, especially: requirement specification with the help of UML use cases and UML state-charts, selection of embedded Linux as a target operating system, management of a request for proposals for the controller unit's main board, development of a proof of concept in C++ on a Linux PC.

Especially, customer assignment at Ericsson, project manager within the Engine Integral Network 1.0 Total Project:

• Development of an ATM switch, AXD 301, based on Solaris + Erlang/OTP, and partly on proprietary hardware (50 people in Sweden). 10 to 160 Gbits/s, ATM, IP, MPLS.
• Development of a VoATM application for AXD 301 (20 developers in Dallas/USA).
• Development and integration of a network management system for Engine Integral Network 1.0 (30 people in Sweden).

Especially:

• Network and operations manager for a pan-European VoIP network.
• Project manager for the establishment of a dial-up Internet service.

Project manager for infrastructure change projects in a telco network.

Network consulting for major French corporations and the public sector.

Implementation, test and integration of a tool for linear transformation of brain PET (Positron Emission Tomography) images. Analysis and adaptation of an algorithm proposed by a Canadian research team. Development in C++ under Silicon Graphics IRIX. Test and integration in PET researchers' work environment. Training of PET researchers in using the tool. Use of IRIS Explorer API for 3D visualising of the images.

Implementation in Python of a compiler for the Jack language, which is a simple general purpose object-oriented programming language. The target language is the ISA of the Hack 16-bit computer, previously built in digital logic.

The compiler is built in several steps:

• An assembler for the Hack assembly language.
• A virtual machine translator, that translates an ad-hoc stack based virtual machine language to Hack assembly.
• A compiler, that translates a Jack program to the virtual machine language. The Jack language has mostly an LL(1) grammar, which allows the implementation of a recursive parser.

Also, an arbitrary non-trivial program was picked, designed and implemented in Jack, as well as an operating system (multiplication and division in software, screen, keyboard and string handling, etc.).

Certificate, grade: 98,4%.

Implementation of a 16-bit computer in digital logic:

• Implementation of a 16-bit ALU in digital logic. The ALU is built in a bottom-up manner with the NAND gate as a starting point.
• Implementation of a 16-bit CPU in digital logic. The CPU is built in a bottom-up manner with the ALU, a D flip-flop, a clock and some previously built logic as a starting point. This includes the implementation of a RAM memory hierarchy that starts at the bit-level. The resulting CPU is called 'Hack'.

Certificate, grade: 100%.